Chip Gallery
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Analog LDO
Process: Samsung 28 nm CMOS
Measurement in progress...
Power-on-Reset Generator
Process: Samsung 28 nm CMOS
Publication:
Digital LDO
Process: TSMC 40 nm CMOS
Publication: 2022 A-SSCC, 2023 TPE
Hybrid LDO
Process: TSMC 65 nm CMOS
Publication: 2022 JSSC
Digital LDO
Process: Samsung 28 nm CMOS
Publication: 2020 ISSCC, 2022 JSSC
Touch Controller AFE
Process: UMC 80 nm HV CMOS
Publication: 2019 ESSCIRC
Touch Controller AFE
Process: TSMC 180 nm RF CMOS
Publication: 2019 JSSC, 2019 ISLPED
Touch Controller AFE
Process: TSMC 180 nm RF CMOS
Publication: 2018 CICC
Touch Controller AFE
Process: TSMC 180 nm GP CMOS
Publication: 2016 ISSCC, 2019 JSSC
Asynchronous SAR ADC
Process: TSMC 180 nm RF CMOS
Publication: 2018 TCAS-II, 2018 EL
Synthesizable SAR ADC
Process: Samsung 28 nm CMOS
Publication: 2019 Access
Noise-Shaping SAR ADC
Process: Samsung 28 nm CMOS
Publication: 2018 A-SSCC, 2022 TVLSI
Delta-Sigma Modulator
Process: Magna/Hynix 180 nm CMOS
Publication: 2017 A-SSCC, 2023 TVLSI
Delta-Sigma Modulator
Process: Samsung 65 nm LP CMOS
Publication: 2017 TCAS-II