Chip Gallery

• Application: Die-to-Die Interfaces    Wireline 

• Publication: [IEEE JSSC'26] An 11.5-Gb/s/pin, 0.4-V Driver-Supply Transmitter With Switched-Coupling Charge-Pump-Based Crosstalk Cancellation for Ultra-Dense Capacitively Coupled Channels

• Significance: Near-complete crosstalk cancellation 

Through the data-dependent joint operation of precharged capacitor coupling and auxiliary feedforward drivers, the 5-channel prototype recovers eye margins of 0.575 UI and 116 mV in the presence of crosstalk from adjacent aggressors with a minimum spacing of 0.4 μm, restoring nearly 100% of the crosstalk-free eye opening, while preserving the original signaling and coding scheme. 

• Application: Cryogenic-to-Room-Temperature Digital Systems    Cryo-CMOS   Power 

• Publication: [IEEE TCAS-II'26] A 1.5-to-300-K Power-on-Reset Circuit With Code-Defined Room-Temperature and Cryogenic Operating Modes in 28-nm CMOS

• Significance: First-reported POR circuit operating from 1.5 K to 300 K

The prototype features a compact resistorless design with an area of less than 0.001 mm², supports programmable POR-level control at room temperature, and achieves a quiescent current of only 17 nA at 1.5 K, providing a low-cost and reliable initialization solution for cryogenic and wide-temperature digital systems.

• Application: Near-threshold Digital Systems    Power  

• Publication: [IEEE TCAS-II'26] A Compact, Low-Power Voltage-Gap-Based Power-on-Reset Circuit With a Programmable Trip Point for Near-VTH Computing Applications

• Significance: Nanowatt-level POR circuit with capacitive voltage-difference generation

The prototype supports low-voltage operation and a wide range of supply ramp times using only regular-VTH MOSFETs, providing a process-portable and energy-efficient POR solution for low-power, low-voltage digital systems.  

• Application: Cryogenic IC Design    Cryo-CMOS  

• Publication: [IEEE TCAD'26] A Geometry-Scalable DC I–V Calibration Methodology for a Commercial Bulk CMOS Process Design Kit for Cryogenic ICs Operating Near 1 K

• Significance: EDA-compatible PDK calibration methodology for cryogenic IC design

By leveraging geometry-dependent parameterization supported by the PSP compact model, the proposed methodology improves DC I–V prediction accuracy near 1 K, facilitating the development of reliable cryogenic ICs for quantum computing and space applications. 

• Application: Wireline Interfaces    Clocking  

• Publication: [IEEE TVLSI'26] A 3.2-GHz Ring-Oscillator-Based Charge-Pump PLL With Time-Domain Optimization of PFD Reset Delay

• Significance: SystemVerilog-based design methodology for optimizing PFD reset delay in CP-PLLs 

By capturing CP current-waveform nonidealities that conventional phase-domain models miss, the proposed method identifies the optimal PFD reset delay and can accelerate low-jitter, low-spur PLL design. 

• Application: Die-to-Die Interfaces    Wireline  

• Publication: [IEEE ESSERC'25] A 0.65-pJ/b, 11-Gb/s/pin Transmitter Employing Edge-Controlled Crosstalk Cancellation for Near-Complete Suppression of Crosstalk-Induced Jitter

• Significance: Near-complete suppression of crosstalk-induced jitter 

Through joint optimization of the XTC driver strength and the edge-control boosting level, the prototype recovers a 0.506-UI eye opening at 11 Gb/s/pin in the presence of adjacent aggressor channels, demonstrating high-density, CIJ-free I/O links for advanced memory and chiplet systems. 

• Application: VLSI systems, Memory Modules    Power  

• Publication: [IEEE TVLSI'25] A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection 

• Significance: Compact, configurable POR circuit with brown-out detection

The prototype demonstrates reliable reset generation over a wide range of supply ramp times from 1 μs to 1 s, with configurable POR level and brown-out detection level, making it suitable for VLSI systems and memory modules. 

• Application: Mobile Display Links    Wireline  

• Publication: [IEEE TVLSI'25] A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces 

• Significance: Energy-efficient embedded-clock display-link transceiver 

By employing a latch-less serializer in the TX and a hybrid CDR with selective digital-loop deactivation in the RX, the prototype TRX demonstrates a 20-Gb/s aggregate data rate with sub-pJ/b/lane energy efficiency for mobile AP-to-TCON interfaces. 

• Application: Multichannel Sensor Interfaces    Data Converter 

• Publication: [IEEE TVLSI'23] An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications 

• Significance: Area/power-efficient DT ΔΣ modulator based on dynamic-boost inverters

By combining compact self-biased dynamic-boost-inverter integrators with a quantitative GBW optimization strategy, the prototype achieves an 84.0-dB peak SNDR and an 87.1-dB DR over a 25-kHz bandwidth in only 0.0939 mm², highlighting its suitability for compact, high-resolution sensor readout systems. 

• Application: IoT Sensor Interfaces    Data Converter  

• Publication: [IEEE TVLSI'22] A Fully-Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques  

• Significance: Mostly-digital noise-shaping SAR ADC 

By combining a second-order fully-passive noise shaping, cyclic DEM, and last-bit majority voting techniques, the prototype achieves an ENOB of 11.2–11.7 bits with a reconfigurable bandwidth of 10–50 kHz at a supply voltage of 0.6–1 V, supporting DVFS-compatible operation for IoT sensor interfaces. 

• Application: System-on-Chips    Power  

• Publication: [IEEE JSSC'22] A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50mV With Fast Settling Time Below 10 ns 

• Significance: First-reported hybrid LDO with sub-50-mV dropout 

Through residue-current-locked joint control of analog and digital LDOs, the prototype achieves a 76-mV voltage droop and an 8.2-ns settling time under a load current step of 80 mA/0.5 ns with a 20-mV dropout voltage, demonstrating high-speed, high-efficiency power regulation for SoCs. 

• Application: Mobile Touchscreens    Sensor Readout  

• Publication: [IEEE ESSCIRC'19] An Always-on 0.53−13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays with Current-Mode Filter and Incremental Hybrid ΔΣ ADC 

• Significance: Always-on mutual-capacitive touchscreen controller 

By combining duty-cycled AFE operation with high-order current-mode filtering and incremental hybrid ΔΣ conversion, the prototype achieves scalable power consumption of 0.53–13.4 mW at a frame rate of 1–120 Hz while maintaining an SNR above 40 dB, enabling low-power touch sensing with robust display-noise immunity for mobile touchscreen systems.