We advance deployable integrated systems through full-custom CMOS IC design, including high-speed interface ICs, data converter ICs, power management ICs, and integrated sensing/computing circuits.

High-Speed Interface ICs

The rapid growth of AI, cloud computing, and chiplet-based heterogeneous systems is driving unprecedented demand for energy-efficient, ultra-high-speed interconnects. In modern AI accelerators and large-scale data center infrastructures, communication bandwidth and energy efficiency have become first-order system bottlenecks. Advanced packaging technologies, such as 2.5D/3D integration and chiplet, have further elevated the importance of high-performance die-to-die interfaces capable of operating at multi-tens to hundreds of gigabits per second per lane with extremely low energy per bit and high bandwidth density.

To enable scalable multi-die and multi-XPU platforms, proprietary high-bandwidth interconnect fabrics are increasingly adopted to deliver low-latency, high-throughput communication across tightly integrated systems. These trends place stringent requirements on high-speed wireline transceivers, PLLs, and CDR circuits, which must provide reliable, low-jitter data communication under severe power, channel loss, crosstalk, supply noise, and signal integrity constraints. Consequently, next-generation interconnect design demands holistic co-optimization across circuits, architecture, and packaging, positioning high-speed interface circuits as a key enabler of future AI and high-performance computing systems.

• Research Interests: High-Speed Wireline Transceiver,  Phase-Locked Loop, Clock and Data Recovery Circuits

• Key Publications: 

  • [IEEE TVLSI 2026] A 3.2-GHz Ring-Oscillator-Based Charge-Pump PLL With Time-Domain Optimization of PFD Reset Delay

  • [IEEE ESSERC 2025] A 0.65-pJ/b, 11-Gb/s/pin Transmitter Employing Edge-Controlled Crosstalk Cancellation for Near-Complete Suppression of Crosstalk-Induced Jitter

  • [IEEE TVLSI 2025] A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces

  • [IEEE TCAS-II 2024] Analysis of Stochastic Phase-Frequency Detector in 2x Oversampling Clock and Data Recovery 

  • [IEEE TCAS-II 2023] A 0.99-pJ/b 10-Gb/s Receiver With Fast Recovery from Sleep Mode Under Voltage Drift 

Data Converter ICs

The evolution of next-generation wireless systems, AI-driven edge intelligence, and advanced sensing platforms is creating increasingly diverse and stringent requirements for mixed-signal interfaces. While emerging communication systems demand higher bandwidth and greater spectral efficiency, intelligent edge and sensor nodes operate under extreme energy and area constraints. Across these applications, scalable signal acquisition with high dynamic range, robustness, and energy efficiency has become a fundamental system challenge.

To address these trends, data converters must simultaneously push performance boundaries, achieving high sampling rates and wide dynamic range, while also enabling ultra-low-power operation for energy-constrained platforms. Addressing this broad design space requires architectural innovation, noise- and mismatch-tolerant techniques, calibration-assisted approaches, and tight analog–digital co-optimization. Advancing energy-efficient data converter design is therefore central to enabling both high-performance communication systems and ultra-low-power intelligent sensing platforms.

• Research Interests: Low-Power, High-Resolution ADC/DAC,  High-Speed ADC/DAC,  Security-Enhanced ADC

• Key Publications:

  • [IEEE TVLSI 2023] An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications 

  • [IEEE TVLSI 2022] A Fully-Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques  

  • [IEEE TCAS-II 2018] A 20 k-to-100kS/s Sub-μW 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-μm CMOS 

  • [IEEE TCAS-II 2017] A 0.4-to-1 V Voltage Scalable ΔΣ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS 

Power Management ICs

The scaling of AI processors, high-performance computing platforms, and intelligent edge systems is significantly increasing the complexity of on-chip power delivery. Modern digital and mixed-signal systems operate under aggressive voltage scaling, fast dynamic workload transitions, and tight energy-efficiency constraints. As supply voltages decrease and current transients become more abrupt, power integrity, including supply noise, voltage droop, and stability, directly impacts timing margins, signal integrity, and overall system reliability. Robust and responsive on-chip regulation has therefore become a critical enabler of both high-performance and ultra-low-power operation.

These trends impose stringent requirements on next-generation low-dropout regulator (LDO) design. Future LDO architectures must achieve fast transient response, low output noise, high power-supply rejection, and stable operation across wide load conditions while maintaining low quiescent current and compact area. Addressing these challenges calls for architectural innovation, adaptive control techniques, and tight analog-digital co-design to deliver scalable, energy-efficient power regulation for advanced computing and sensing systems.

• Research Interests: Analog/Digital/Hybrid Low-Dropout Regulator, Power Control & Monitoring Circuit 

• Key Publications:

  • [IEEE TVLSI 2025] A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection 

  • [IEEE TPE 2024] A Capacitorless External-Clock-Free Fully-Synthesizable Digital LDO With Time-Based Load-State Decision and Asynchronous Recovery 

  • [IEEE JSSC 2023] An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector 

  • [IEEE JSSC 2022] A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50mV With Fast Settling Time Below 10 ns 

  • [IEEE ISSCC 2020] A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density