Research Interests: Cryogenic IC Design Methodology, Cryo-CMOS ADC/DAC/LDO/PLL
Publications:
[IEEE TCAS-II 2026] A 1.5-to-300-K Power-on-Reset Circuit With Code-Defined Room-Temperature and Cryogenic Operating Modes in 28-nm CMOS
[IEEE TCAD 2026] A Geometry-Scalable DC I–V Calibration Methodology for a Commercial Bulk CMOS Process Design Kit for Cryogenic ICs Operating Near 1 K
