Cryogenic ICs

Quantum computers, space instruments, and ultra-sensitive detectors operate at temperatures from a few kelvin down to the millikelvin range, where control and readout electronics have traditionally stayed at room temperature and connected to the cold stage through long cables. As qubit counts grow from tens to thousands, this approach runs into hard limits on wiring, heat load, and latency. Placing CMOS control and interface circuits inside the cryostat, close to the qubits, is widely viewed as the path to scalable quantum systems, but it requires circuits that work reliably at temperatures far outside the range for which commercial processes are characterized.

Designing at cryogenic temperatures changes the transistor itself: threshold voltages shift, subthreshold slopes steepen, mobility rises, and effects such as kink and hysteresis appear, none of which standard foundry models capture. Our work addresses this challenge from two directions, developing calibration methodologies that make commercial process design kits usable near 1 K within standard EDA flows, and designing circuit building blocks, including power-on-reset, LDO, ADC/DAC, and PLL, that operate across the full range from room temperature to deep cryogenic conditions with minimal power dissipation in the cold stage. Together, these efforts aim to make cryogenic CMOS a practical, reliable foundation for quantum computing and other extreme-environment systems.

• Research Interests: Cryogenic IC Design Methodology, Cryo-CMOS ADC/DAC/LDO/PLL

• Publications: 

  • [IEEE TCAS-II 2026] A 1.5-to-300-K Power-on-Reset Circuit With Code-Defined Room-Temperature and Cryogenic Operating Modes in 28-nm CMOS

  • [IEEE TCAD 2026] A Geometry-Scalable DC I–V Calibration Methodology for a Commercial Bulk CMOS Process Design Kit for Cryogenic ICs Operating Near 1 K