Power Management ICs

The scaling of AI processors, high-performance computing platforms, and intelligent edge systems is significantly increasing the complexity of on-chip power delivery. Modern digital and mixed-signal systems operate under aggressive voltage scaling, fast dynamic workload transitions, and tight energy-efficiency constraints. As supply voltages decrease and current transients become more abrupt, power integrity, including supply noise, voltage droop, and stability, directly impacts timing margins, signal integrity, and overall system reliability. Robust and responsive on-chip regulation has therefore become a critical enabler of both high-performance and ultra-low-power operation.

These trends impose stringent requirements on next-generation low-dropout regulator (LDO) design. Future LDO architectures must achieve fast transient response, low output noise, high power-supply rejection, and stable operation across a wide range of load conditions while maintaining low quiescent current and compact area. Addressing these challenges calls for architectural innovation, adaptive control techniques, and tight analog-digital co-design to deliver scalable, energy-efficient power regulation for advanced computing and sensing systems.

• Research Interests: Analog/Digital/Hybrid Low-Dropout Regulator, Power Control & Monitoring Circuit 

• Publications:

  • [IEEE TCAS-II 2026] A 1.5-to-300-K Power-on-Reset Circuit With Code-Defined Room-Temperature and Cryogenic Operating Modes in 28-nm CMOS

  • [IEEE TCAS-II 2026] A Compact, Low-Power Voltage-Gap-Based Power-on-Reset Circuit With a Programmable Trip Point for Near-VTH Computing Applications 

  • [IEEE TVLSI 2025] A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection 

  • [IEEE TPE 2024] A Capacitorless External-Clock-Free Fully-Synthesizable Digital LDO With Time-Based Load-State Decision and Asynchronous Recovery 

  • [IEEE JSSC 2023] An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector 

  • [IEEE JSSC 2022] A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50mV With Fast Settling Time Below 10 ns 

  • [IEEE ISSCC 2020] A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density 

Data Converter ICs

The evolution of next-generation wireless systems, AI-driven edge intelligence, and advanced sensing platforms is creating increasingly diverse and stringent requirements for mixed-signal interfaces. While emerging communication systems demand higher bandwidth and greater spectral efficiency, intelligent edge and sensor nodes operate under extreme energy and area constraints. Across these applications, scalable signal acquisition with high dynamic range, robustness, and energy efficiency has become a fundamental system challenge.

To address these trends, data converters must simultaneously push performance boundaries, achieving high sampling rates and wide dynamic range, while also enabling ultra-low-power operation for energy-constrained platforms. Addressing this broad design space requires architectural innovation, noise- and mismatch-tolerant techniques, calibration-assisted approaches, and tight analog–digital co-optimization. Advancing energy-efficient data converter design is therefore central to enabling both high-performance communication systems and ultra-low-power intelligent sensing platforms.

• Research Interests: Low-Power, High-Resolution ADC/DAC,  High-Speed ADC/DAC,  Security-Enhanced ADC

• Publications:

  • [IEEE TVLSI 2023] An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications 

  • [IEEE TVLSI 2022] A Fully-Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques  

  • [IEEE TCAS-II 2018] A 20 k-to-100kS/s Sub-μW 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-μm CMOS 

  • [IEEE TCAS-II 2017] A 0.4-to-1 V Voltage Scalable ΔΣ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS 

Sensor Readout ICs

• Research Interests: Energy-Efficient, High-Fidelity, Smart Analog Front-End for Sensor Interfaces

• Publications: 

  • [IEEE ESSCIRC 2019] An Always-on 0.53−13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays with Current-Mode Filter and Incremental Hybrid ΔΣ ADC 

  • [IEEE JSSC 2019] A Mutual Capacitance Touch Readout IC With 64% Reduced-Power Adiabatic Driving Over Heavily Coupled Touch-Screen 

  • [IEEE JSSC 2019] A Noise-Immunity-Enhanced Analog Front-End for 36×64 Touch-Screen Controllers With 20-VPP Noise Tolerance at 100kHz 

  • [IEEE ISSCC 2016] A 100-TRX-Channel Configurable 85-to-385Hz-Frame-Rate Analog Front-End for Touch Controller with Highly Enhanced Noise Immunity of 20Vpp