High-Speed ICs

The rapid growth of AI, cloud computing, and chiplet-based heterogeneous systems is driving unprecedented demand for energy-efficient, ultra-high-speed interconnects. In modern AI accelerators and large-scale data center infrastructures, communication bandwidth and energy efficiency have become first-order system bottlenecks. Advanced packaging technologies, such as 2.5D/3D integration and chiplet, have further elevated the importance of high-performance die-to-die interfaces capable of operating at multi-tens to hundreds of gigabits per second per lane with extremely low energy per bit and high bandwidth density.

To enable scalable multi-die and multi-XPU platforms, proprietary high-bandwidth interconnect fabrics are increasingly adopted, placing stringent requirements on wireline transceivers, PLLs, and CDR circuits that must deliver low-jitter data under severe power, channel loss, crosstalk, and supply noise constraints. Our work targets the dense, short-reach links where these constraints are tightest. We develop die-to-die transmitters that cancel crosstalk between closely spaced channels through feedforward compensation, recovering a nearly crosstalk-free eye without changing the signaling or coding scheme, as well as energy efficient display link transceivers with reference-less clock and data recovery. On the clocking side, we build time-domain design methodologies that capture circuit nonidealities missed by conventional phase-domain models, enabling faster optimization of low-jitter, low-spur PLLs. These efforts position high-speed interface design as a key enabler of chiplet based AI and high-performance computing systems.

Research Interests: High-Speed Wireline Transceiver, Phase-Locked Loop, Clock and Data Recovery Circuits
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