High-Speed Interface ICs

The rapid growth of AI, cloud computing, and chiplet-based heterogeneous systems is driving unprecedented demand for energy-efficient, ultra-high-speed interconnects. In modern AI accelerators and large-scale data center infrastructures, communication bandwidth and energy efficiency have become first-order system bottlenecks. Advanced packaging technologies, such as 2.5D/3D integration and chiplet, have further elevated the importance of high-performance die-to-die interfaces capable of operating at multi-tens to hundreds of gigabits per second per lane with extremely low energy per bit and high bandwidth density.

To enable scalable multi-die and multi-XPU platforms, proprietary high-bandwidth interconnect fabrics are increasingly adopted to deliver low-latency, high-throughput communication across tightly integrated systems. These trends place stringent requirements on high-speed wireline transceivers, PLLs, and CDR circuits, which must provide reliable, low-jitter data communication under severe power, channel loss, crosstalk, supply noise, and signal integrity constraints. Consequently, next-generation interconnect design demands holistic co-optimization across circuits, architecture, and packaging, positioning high-speed interface circuits as a key enabler of future AI and high-performance computing systems.

Research Interests: High-Speed Wireline Transceiver, Phase-Locked Loop, Clock and Data Recovery Circuits
Publications:

Page updated

Google Sites

Report abuse